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ICs for Consumer Electronics
SRC-Scan Rate Converter SDA 9255
Data Sheet 1998-02-01
Edition 1998-02-01 This edition was realized using the software system FrameMaker(R) Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 8.2.98. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
ICs for Consumer Electronics
Scan Rate Converter SDA 9255
Data Sheet 1998-02-01
SDA 9255 Revision History: Previous Version: Page Page (in previous (in current Version) Version)
Current Version: 1998-02-01 1997-07-01 Subjects (major changes since last revision)
Definition of N.C. pins
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA = 25C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit.
Edition 1998-02-01 Published by Siemens AG, Semiconductor Group Copyright (c) Siemens AG 1997. All rights reserved. Terms of delivery and right to change design reserved.
SDA 9255
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 3 3.1 3.2 4 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
Page 5 5 5 6 7 8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input Timing and Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Delay of Vertical Input Synchronization Signal . . . . . . . . . . . . . . . . . . . . . . 11 Number of Active Lines of an Input Field . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Number of Not Active Lines of an Input Field . . . . . . . . . . . . . . . . . . . . . . . . 12 Not Active Pixels of Input Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Timing and Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Number of Not Active Lines of Output Field . . . . . . . . . . . . . . . . . . . . . . . . . 14 Number of Not Active Pixels of Output Field . . . . . . . . . . . . . . . . . . . . . . . . 15 VOUT, HOUT and HREF Signal Length . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Synchronization Raster and Interlaced Output Signal . . . . . . . . . . . 16 Motion Adaptive Temporal Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . 17 Digital Vertical Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-Bus Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Characteristics (Assuming Recommended Operating Conditions) . . . . 34 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Timing of the SDA 9255 (HSINP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . Output Timing of the SDA 9255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Vertical Synchronization Signal (VSINP = 0) . . . . . . . . . . . . . . . . . Example for Not Active Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for Not Active Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for Not Active Output Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing for HOUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing for VOUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing for HREF Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
36 36 37 37 38 38 39 39 40 40
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1998-02-01
SDA 9255
Table of Contents 5.10 5.11 5.12 5.13 6
Page 41 41 42 42
Example for INTERLACED Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Timing START/STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Timing DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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SRC-Scan Rate Converter
SDA 9255
CMOS 1 1.1 * * * * * * * * * * * * * Overview Features
100/120 Hz interlaced scan conversion Data format 4:1:1 On chip field memory Digital vertical zooming P-MQFP-64-1 Digital vertical panning Motion adaptive temporal noise reduction, field based Still field Color difference input data representation 2's complement or unsigned Color difference output data representation 2's complement or unsigned Sync Generation for backend IC I2C-Bus control (400 kHz) P-MQFP-64 package 5 V 5 % supply voltage General Description
1.2
The SDA 9255 is a new component of the Siemens MEGAVISION(R) IC set. The SDA 9255 comprises some of the functionalities of the MEGAVISION(R) IC's SDA 9220 (Memory Sync Controller) and SDA 9254 (Triple TV-SAM plus Noise Reduction) and can therefore be used as a low cost digital featurebox.
Type SDA 9255
Semiconductor Group
Ordering Code Q67101-H5190
5
Package P-MQFP-64-1
1998-02-01
SDA 9255
1.3
Pin Configuration
TESTI3
TESTI2
YIN0 VSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 YIN7 TEST LL2CLK TESTO7 TESTO8 TESTO9 VSS 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TESTI0 RESET SYNCEN TESTO6 TESTO5 TESTO4 VSS
VDD VSS
LL2CLK INTERLACED HOUT VOUT HREF YOUT7 YOUT6
VDD
TESTI1
UVIN7
UVIN6
UVIN5
UVIN4
YIN6
YIN5
YIN4
YIN3
YIN2
YIN1
SDA 9255
VDD VSS
HIN VIN SDA SCL TESTIN TESTEN TESTO3
TESTO1
YOUT2
VDD
UVOUT6
UVOUT5
UVOUT7
UVOUT4
TESTO0
TESTO2
YOUT5 VSS
YOUT4
YOUT3
YOUT1
YOUT0 VSS
Figure 1
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UEP10014
SDA 9255
1.4
Pin Description Name Type S S I/TTL I/TTL I/TTL I/TTL Description Supply voltage (VSS = 0 V) Supply voltage (VDD = 5 V) Data input Y (see data format) Data input UV (see data format) Synchronization enable input System reset. The RESET input is low active. In order to ensure correct operation a "Power On Reset" must be performed. The RESET pulse must have a minimum duration of two clock periods of the system clock (LL2CLK). H-Sync input V-Sync input
Pin No.
2,8,24,26,41,55, VSS 57 9,25,40,56 42,...,49 36,...,39 30 31
VDD
YIN0 ... 7 UVIN4 ... 7 SYNCEN RESET
23 22 21 20 19 18 13,...,10 7,...,3,1,64,63 62 61 60 59 58,51 50 27,28,29, 52,53,54 14,15,16,17 32,33,34,35 S: supply,
HIN VIN SDA SCL TESTIN TESTEN UVOUT4 ... 7 YOUT0 ... 7 HREF VOUT HOUT
I/TTL I/TTL I/O I I/TTL I/TTL O/TTL O/TTL O/TTL O/TTL O/TTL
INTERLACED O/TTL LL2CLK TEST TESTO 4...9 TESTO 0...3 TESTI 0...3 I: input, O: output, I/TTL I/TTL O O I
I2C-Bus data line I2C-Bus clock line Test input, connect to VSS for normal operation Test enable input, connect to VSS for normal operation Data output UV (see data format) Data output Y (see data format) Horizontal active video output V-Sync output H-Sync output Interlace signal for AC coupled vertical deflection System clock Test input, connect to VSS for normal operation Do not connect, Pins have to be left open
Not used output stages, do not connect to any other driver, VSS or VDD ; Pins can be left open Input stages (internal pull-down); Pins can be left open
TTL: digital (TTL)
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SDA 9255
1.5
Block Diagram
VDD
VSS
SDA
SCL
2 C-Bus Interface Memory Controller Field Memory Upconversion Vertical Zooming Panning YOUT Form UVOUT
INTERLACED UVIN YIN Reform Noise Reduction HOUT Sync Signal Generator VOUT HREF
HIN
VIN SYNCEN
Figure 2
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UEB10013
SDA 9255
2
System Description
The device generates at its output an opportune sequence of 100/120 Hz fields () [50/60 Hz frames ()] derived by processing the field A or B which is stored in one internal field memory. The fields can be noise reduced and vertically zoomed. Additionally the device generates a vertical sync pulse, a horizontal sync pulse and a horizontal reference signal (horizontal active video output) in phase with the output data. Furthermore an interlace signal for AC coupled vertical deflection is available. 2.1 Input Data Formats
The SDA 9255 accepts at the input side the following input format (relations of Y : (B-Y) : (R-Y) : 4 : 1 : 1). The representation of the samples of the chrominance signal is programmable as positive dual code (unsigned) or two's complement code (TWOIN, TWOOUT, subaddress 00H, see description of I2C Bus). Data Pin YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 UVIN7 UVIN6 UVIN5 UVIN4 XAB: SDA 9255 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 X: signal component, Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 A: sample number, Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 B: bit number Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00
The amplitude resolution for each input signal component is 8 Bit, the maximum clock frequency is 27 MHz.
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2.2 Data Pin
Output Data Formats
YOUT7 YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 YOUT1 YOUT0 UVOUT7 UVOUT6 UVOUT5 UVOUT4 XAB: 2.3
Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 A: sample number,
Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 B: bit number
Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00
X: signal component,
Input Timing and Parameter
The SDA 9255 has five input signals: HIN VIN SYNCEN YIN0 ... 7 Pin 23 Pin 22 Pin 30 Pin 42, 43, 44, 45, 46, 47 ,48, 49 Horizontal synchronization signal - low or high active Vertical synchronization signal - low or high active Enable signal for HIN and VIN signal, low active Luminance input Chrominance input
UVIN4 ... 7 Pin 36, 37, 38, 39
The SDA 9255 includes a V-Sync delay block.This is implemented to make sure that the field identification is working correctly. This is briefly described below. The phase relation of the incoming horizontal synchronization signal (HIN) and the incoming data for HSINP = 0 and VSINP = 0 is shown in figure 7 (see chapter 5.1, Input Timing of the SDA 9255 (HSINP = 0)). The SDA 9255 needs the synchronization enable input (SYNCEN) which is used to gate HIN and VIN. This is implemented for frontends which are working with 13.5 MHz and a large output delay time for H-Sync and
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V-Sync (e.g. Intermetall VPC3200A, output delay: 35 ns). For this application the half system clock (13.5 MHz) from the frontend should be provided at this pin. In case the frontend is working at 27.0 MHz with sync signals whose delay time are smaller than 25 ns, this input can be set to low level (SYNCEN = VSS) (e.g. Siemens SDA 9257, SDA 9206, output delay: 25 ns). Thus the falling edge of HIN signal is detected when the SYNCEN input is low. The incoming HIN (and VIN) is sampled with the system clock (LL2CLK = 27.0 MHz). The register value HSDLY and MCNAPIP (subaddress 0BH and 0CH, see description of I2C Bus) have to be adjusted in the way that the distance from the falling edge of the HIN to the first active pixel is correct. The half, quarter and eighth system clock is also shown in this diagram. They are generated inside the SDA 9255. The half system clock (LL_CLK = 13.5 MHz) is used to sample the incoming YUV data and run some blocks inside the SDA 9255. The quarter system clock (LH_CLK = 6.75 MHz) is used to run some blocks inside the SDA 9255. The eighth system clock (LQ_CLK = 3.375 MHz) is used to synchronize the 4:1:1 input data stream. The setting of the register HSDLY and MCNAPIP is explained in chapter 1. The SDA 9255 has a fixed number of active pixels per input line. It is fixed to 720 luminance pixels and 180 chrominance pixels. 2.3.1 Delay of Vertical Input Synchronization Signal In order to have always the same raster of the vertical and horizontal synchronization signal inside the SDA 9255 it is possible to shift the V-Sync signal. The subaddress 09H of the SDA 9255 (VSDLY, see description of I2C Bus) controls the shift of the V-Sync. The user has to know the input sync raster and then the user can adjust the VSDLY register value in the way that the field identify circuit inside the SDA 9255 can work properly. The adjustment of the V-Sync can be done in steps of 32 clock periods (LL2CLK). Thus the delay is also dependent on the system clock frequency. The formula to calculate the delay is shown below. DELAY (VIN to VS_int) = (VSDLY * 32 + 7 ... 11) * TLL2CLK where: VIN: VS_int: TLL2CLK : Incoming V-Sync at pin 22; VSDLY: is the register value Internal V-Sync System clock period (e.g 1/27.0 MHz = 37.04 ns)
The initial delay (7 ... 11 system clocks) is caused by flip-flops at the input. This delay is not a fixed number, because a quarter of the system clock (LH_CLK) is used to set the delay. The phase of the LH_CLK is dependent on the RESET and the SYNCEN (see figure 7). An example shows figure 9 (see chapter 5.3, Internal Vertical Synchronization Signal (VSINP = 0)). In this example the falling edge of the VIN signal of field A is at 35 s and the falling edge of the VS_int signal is at 16 s (both signals are related to the falling
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edge of the previous HS_int, compare chapter 1). Thus the sampling points of the field identify circuit (marked in the diagram with a" and b") have uniform distances to the falling edge of the VS_int. The falling edge of the VIN signal of field B is at 3 s and the falling edge of the VS_int signal is at 48 s (related to the falling edge of the previous HIN). Here the sampling points have also uniform distances to the falling edge of the VS_int signal. The user should adjust this value carefully. Dependent on the input mode of the frontend circuit the integration time of the V-Sync can change. For non-standard signals, for instance, a shorter integration time may be chosen. The internal V-Sync (VS_int) must have the falling edge at line 2 for field A. All the other settings (NALIP ...) are dependent on this internal V-Sync. The default setting of the VSDLY is 3AH. This corresponds to a delay of about 69 s (58 (= 3AH) * 32 * 37 ns), which suits for the clock sync generator SDA 9257 and SDA 9206. 2.3.2 Number of Active Lines of an Input Field The subaddress 0AH (AL, see description of I2C Bus) is used to adjust the number of active lines per input and output field. It is independent of the MODE10050 in subaddress 00H. The register value AL has to be chosen in the following way: Number of lines per field - 2 288 - 2 AL = ------------------------------------------------------------------------- ; e.g. ------------------ = 143 2 2 2.3.3 Number of Not Active Lines of an Input Field Due to the fact that the SDA 9255 stores only the active field in the field memory, it requires the information of the start of the active field and the active line. A not-activeline counter (NALIP, subaddress 0BH, see description of I2C Bus) starts counting the incoming H-Syncs when it detects a falling edge of the VS_int signal. If VS_int is adjusted as recommended in the explanation of subaddress 09H then the calculation of the NALIP value can be done in the following way: NALIP = first active line of field A - 5 (e.g. 23 - 5 = 18) In figure 10 (see chapter 5.4, Example for Not Active Input Register) an example for NALIP = 18 is shown. As you can see for field A 21 H-Syncs are counted and for field B 22 H-Syncs are counted. If NALIP is set to '0' line 5 is the first active line of field A and line 318 the first active line of field B (318 - 5 = 313). The difference between first active line of field B and field A should be:
= (No.lines per frame DIV 2) + 1; e.g. = 625 DIV 2 + 1 = 313
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2.3.4 Not Active Pixels of Input Field In the SDA 9255 an H-Sync delay circuit is implemented. The output of this block is the HS_int. The distance of the incoming H-Sync (HIN, falling edge for HSINP = 0) and the active data is adjustable by the HSDLY register value and the MCNAPIP register value (subaddress 0BH and 0CH, see description of I2C Bus). With the HSDLY register the delay of the external (HIN) to the internal H-Sync (HS_int) is adjustable. DELAY (HIN to HS_int) = (HSDLY * 64 + 4) * TLL2CLK This internal H-Sync (HS_int) is fed to the memory control unit. The MCNAPIP (memory controller not active pixel at input) is used to adjust the distance to the active line in steps of one system clock period. So the MCNAPIP is used to set the phase of the internal generated clocks LL_CLK, LH_CLK and LQ_CLK. DELAY (HS_int to active data) = (MCNAPIP + 61) * TLL2CLK The total distance of the falling edge of the incoming H-Sync (HIN, falling edge for HSINP = 0) to the active data of the line is: DELAY (HIN to active data) = (HSDLY * 64 + MCNAPIP + 65) * TLL2CLK In the formula above you can see that the first active pixel occurs 65 system clocks after the falling edge of the HIN signal, if HSDLY and MCNAPIP are set to zero. In the figure 7 (see chapter 5.1, Input Timing of the SDA 9255 (HSINP = 0)) the input timing of the SDA 9255 is shown. The luminance and chrominance data are coming with half the system clock speed (e.g. 13.5 MHz). The SDA 9255 accepts the YIN data every second edge of the LL2CLK clock; in the SDA 9255 the luminance and chrominance data are sampled with the rising edge of the internal LL_CLK, which is half the system clock (e.g. 13.5 MHz). At the position of the first active pixel the phase of the half system clock (LL_CLK = 13.5 MHz), the quarter system clock (LH_CLK = 6.75 MHz) and the eighth system clock (LH_CLK = 3.375 MHz) is always as shown in the diagram. The LL_CLK is used for sampling the incoming data. The LQ_CLK is used to synchronize the 4:1:1 data stream.
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SDA 9255
2.4
Output Timing and Parameter
The SDA 9255 has six output signals: HOUT VOUT HREF YOUT0 ... 7 UVOUT4 ... 7 Pin 60 Pin 61 Pin 62 Horizontal synchronization signal - high active Vertical synchronization signal - high active Horizontal active video output Interlace signal Chrominance output
INTERLACED Pin 59 Pin 13, 12, 11, 10
Pin 7, 6, 5, 4, 3, 1, 64, 63 Luminance output
There are different modes of output synchronization raster possible. The data output signal of the SDA 9255 (YOUT, UVOUT and HREF) are fed to the digital-to-analog converter. The timing of the output signals is given in figure 8 (see chapter 5.2, Output Timing of the SDA 9255). 2.4.1 Number of Not Active Lines of Output Field The register values NALOP and NAPOP are used to set the position of the active output field on the screen. To do this the register value to align the not active lines (NALOP, subaddress 0DH, see description of I2C Bus) and the register value to align the not active pixels (NAPOP, subaddress 0EH, see description of I2C Bus) for the output signal are available. To change the vertical position of the picture on the screen the NALOP register can be utilized. The NALOP register (not active lines for output) is used to adjust the number of not active output lines in steps of two lines in case of 100/120 Hz interlaced and in steps of four lines in case of 50/60 Hz proscan. To calculate the first active output line the following formula can be used: for MODE10050 = 0 ==> 100/120 Hz interlaced: FAOPL = NALOP * 2 + 3 for MODE10050 = 1 ==> 50/60 Hz proscan: FAOPL = NALOP * 4 + 5 where FAOPL: NAL_OP: The first active output line Register value
The maximum value for the first active line is 65 for 100/120 Hz and 129 for 50/60 Hz. In figure 11 (see chapter 5.5, Example for Not Active Output Register) an example for the setting of the NALOP register is shown. The synchronization output (HOUT,
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VOUT, HREF) signals are high active. In the example the register value is 10 and the mode is '0' (100/120 Hz/interlaced). FAOPL = NALOP * 2 + 3 = 10 * 2 + 3 = 23 So line 23 is the first active output line. For proper operation the number of not active lines at output side plus the number of active lines have to be smaller than the total number of lines. The following formula should be true. NALOP * 2 + AL * 2 + 3 (No. of lines per frame) DIV 2 (e.g. 312) where AL: NALOP: Register value Register value
2.4.2 Number of Not Active Pixels of Output Field To change the horizontal position of the picture on the screen the NAPOP register value can be utilized. The not active pixels for output register ( NAPOP ) is used to adjust the number of not active output pixels of a line. The register value is multiplied by '4' and has an initial value of 9 ... 12 (HSODLY = 0), depending on the MCNAPIP setting (subaddress 0BH and 0CH, see description of I2C Bus). FAOPP = NAPOP * 4 + 9 ... 12 - HSODLY = 0 FAOPP = NAPOP * 4 + (- 163) ... (- 160) ; HSODLY = 1 is equal to : FAOPP = NAPOP * 4 + 9 ... 12 - 172 * HSODLY where FAOPP: NAPOP: HSODLY: The first active output pixel after rising edge of HOUT Register value Register value
The time from the rising edge of the HOUT signal to the first active output pixel can be calculated in the following way:
tNAPOP = ( NAPOP * 4 + 9 ... 12 ) * tLL2CLK ; HSODLY = 0 tNAPOP = (NAPOP * 4 + (- 163) ... (-160)) * tLL2CLK ; HSODLY = 1
where
tNAPOP : Time from rising edge of HOUT to first active output pixel tLL2CLK : System clock period (e.g. 1/27 MHz)
figure 12 (see chapter 5.6, Example for Not Active Output Pixels) shows the effect of the register NAPOP.
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SDA 9255
2.4.3 VOUT, HOUT and HREF Signal Length The length of the output synchronization signals (HOUT, VOUT) is fixed. The HOUT signal is active high with a length of 32 system clocks (27.0 MHz) which corresponds to a length of 1.185 s. The VOUT signal is also active high with a length of 2 output lines. So in case of PAL B/G the active high period of the VOUT lasts for 64 s (see figure 13, Timing for HOUT Signal and figure 14, Timing for VOUT Signal). The HOUT signal of the SDA 9255 can be delayed by a fixed value of 172 system clocks (27.0 MHz) by setting the HSODLY bit of subaddress 0FH to '1'(see description of I2C Bus). The number of active pixels per line is constant 720 pixels. The HREF output signal (pin 62) indicates the active part of the output lines. The length is also constant (720 system clocks). During the vertical and horizontal blanking period this signal is low. The timing is shown in figure 15 (see chapter 5.9, Timing for HREF Signal). The chrominance output format is like the output format as described in chapter 1. 2.4.4 Output Synchronization Raster and Interlaced Output Signal The output synchronization and data raster in 100/120 Hz mode can be set by the MODESYNC register value (subaddress 01H, see description of I2C Bus). In case of MODE10050 = 1 (50/60 Hz pro-scan mode) this register value has no effect. The interlaced signal INTERLACED (pin 59) is a control signal which may be used to control an AC coupled vertical deflection unit. If the MODESYNC register value (subaddress 01H, see description of I2C Bus) is set to AABB mode, where field 2 and 3 have to be shifted down (MODESYNC = 10). For this the interlaced register INTL (subaddress 0DH and 0EH, see description of I2C Bus) must be set to 0110. In figure 16 (see chapter 5.10, Example for INTERLACED Signal) an example for the INTL register value is shown. Bit zero defines the output for the first field (field A); bit one defines the output for the second field (field A); bit two defines the output of the third field (field B); bit three defines the output of the fourth field (field B). So if the bit is set to zero then the output is low and if the bit is set to one then the output is high. For DC coupled vertical deflection the INTERLACED signal is not required.
Semiconductor Group
16
1998-02-01
SDA 9255
2.5
Motion Adaptive Temporal Noise Reduction
YIN/UVIN + +
Field Memory +
*
k-factor
NRKF0 NRKF1 NRKF2 NRKF3
LUT
Address
MDFORNR
Figure 3 Block Diagram of Noise Reduction The diagram above shows a block diagram of the motion adaptive noise reduction. The noise reduction in the luminance path has the same structure as the noise reduction in the chrominance path. Subaddresses 02H and 03H (NRKF0, NRKF1, NRKF2, NRKF3, see description of I2C Bus) are used to align the filter coefficients of the noise reduction IIR filter. Four different k-factors NRKF0 ... 3 can be modified which are fed to the multiplier of the IIR filter. Depending on the output of the motion detection for noise reduction (MDFORNR) the corresponding k-factor NRKF0 ... 3 is used for the IIR filter (see the table below).
Semiconductor Group
17
1998-02-01
UEB10015
SDA 9255
Table 1 MDFORNR and Corresponding k-Factor MDFORNR 0 1 2 3 k-Factor NRKF0 NRKF1 NRKF2 NRKF3 Mode Still Quasi still Quasi motion Motion
For NRKF0 ... 3 values between 0 and 7 can be chosen. The following table shows the theoretical amount of noise reduction dependent on the applied k-factor. Table 2 Filter Coefficients Dependent on the k-Factor k-Factor 0 1 2 3 4 5 6 7 Amount of NR 0 dB 1.1 dB 2.2 dB 3.4 dB 4.8 dB 6.4 dB 8.5 dB 11.8 dB
The subaddresses 04H, 05H and 06H (MDNRTH0, MDNRTH1, MDNRTH2, see description of I2C Bus) are used to align the motion detection for noise reduction (MDFORNR). The sensitivity of the motion detection is influenced by changing the threshold levels of the motion values. A rough block diagram of the motion detection for noise reduction is shown below.
Semiconductor Group
18
1998-02-01
SDA 9255
YIN +
Noise Reduction
Field Memory
DYIN MDNRTH0 MDNRTH1 MDNRTH2
Low Pass Filter
1 MUX 0
ABS
LIMITER
THRESHOLD
0 MDFORNR MUX
FNR
1
NRHF
SNR
Figure 4 Block Diagram of Motion Detection for Noise Reduction The input signals for the motion detection for noise reduction are the just incoming luminance signal (YIN) and the already noise reduced luminance signal on one field delay (DYIN). Both signals are fed to a subtractor, followed by a low pass filter. This filter can be bypassed by setting the NRHF bit (see description subaddress 08H, Bit 0) to '0'. The absolute value is calculated and given to a limiter block. The output signal is fed to the threshold block, where the value is quantized by using the 3 threshold values MDNRTH0, MDNRTH1 and MDNRTH2. The quantization characteristic of the threshold block is shown by the following table and diagram. Table 3 Quantization Table of MDFORNR Input Value 0 ... (TH0 - 1) TH0 ... (TH1 - 1) TH1 ... (TH2 - 1) TH2 ... 31 Output 0 1 2 3 Mode Still Quasi still Quasi motion Motion
Semiconductor Group
19
1998-02-01
UEB10016
SDA 9255
3 2 1 0
~ ~
0
MDNRTH0
MDNRTH1
MDNRTH2
31
UEB10017
Figure 5 Quantization Characteristic of MDFORNR The following table shows an example for noise reduction settings. These five settings could be implemented and the customer can choose, which he prefers. For example, to have a subjective impression of medium noise reduction of the picture, you have to set the k-factors: NRKF0 = 4, NRKF1 = 3, NRKF2 = 2, NRKF3 = 0 and MDNRTH0 = 4, MDNRTH1 = 8 and MDNRTH2 = 12. Table 4 Example for Noise Reduction Settings Amount of Noise Reduction Parameter NRKF0 NRKF1 NRKF2 NRKF3 MDNRTH0 MDNRTH1 MDNRTH2 No 0 0 0 0 don't care don't care don't care Slightly 3 2 1 0 2 6 10
20
Medium 4 3 2 0 4 8 12
Strong 7 4 2 0 4 10 14
Heavy 7 5 3 1 4 10 16
1998-02-01
Semiconductor Group
SDA 9255
2.6
Digital Vertical Zooming and Panning
The user can choose 17 different zoom factors and 37 pan factors. Every zoom factor can be used without considering other register values, but on the other hand the pan factor is very much dependent on the zoom factor. So be careful in choosing the pan factor. In the following table the zoom factor (subaddress 0FH, see description of I2C Bus) and the corresponding visual zoom of the input field is shown. In the third column the required number of input lines is shown, when the number of displayed output lines is 288. The fourth column shows the allowed value PAN value (subaddress 10H, see description of I2C Bus) and the last column the PAN register value for vertical centre position. Table 5 Table of Zoom Factors and Panning Factors Zoom 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Visual Zoom 1 1.03 1.06 1.10 1.14 1.18 1.23 1.28 1.33 1.39 1.45 1.52 1.6 1.68 1.77 1.88 2.0 NoIPL (NoOPL = 288) 288 279 270 261 252 243 234 225 216 207 198 189 180 171 162 153 144 Panning Range Centre Panning PAN PAN 0 0 ... 2 0 ... 4 0 ... 6 0 ... 9 0 ... 11 0 ... 13 0 ... 15 0 ... 18 0 ... 20 0 ... 22 0 ... 24 0 ... 27 0 ... 29 0 ... 31 0 ... 33 0 ... 36 0 1 2 3 4 5 6 7 8 10 11 12 13 14 15 17 18
Dependent on the zoom factor the SDA 9255 requires a certain number of input lines of a field.
Semiconductor Group
21
1998-02-01
SDA 9255
ZOOM x 2 + 32 NoIPL = NoOPL x ----------------------------------------64 where NoIPL: NoOPL: ZOOM: Number of required input lines Number of generated output lines (AL * 2) + 2 Register value (0 ... 16)
In the third column of the table above the required number of input lines is shown, if the generated number of output lines is 288 (AL = 143). In the last row you can see that for the visual zoom factor of 2 half the number of input lines is necessary, which is of course obvious. As mentioned before, only zoom factors between '0' and '16' are allowed. If factors bigger than 16 are chosen, they are set to '16'. Panning is possible in steps of 4 input lines. So the first active input line which is used to generate the first active output line can be calculated in the following way: FAIPL = PAN * 4 + 1 where FAIPL: First active input line to generate the first active output line PAN: Register value With PAN = 0 the first active input line is line 1, as expected. In case of PAN = 1 the first active input line is line 5, etc. So the allowed register value for pan can be calculated from the last column of the table above. In this example with 288 active lines and, for instance, zoom factor of '15', the maximum pan factor is '2'. Pan = '3' is permitted which can be seen by this calculation: 3 * 4 + 279 = 291. The required number of input lines plus the panning lines is larger than the actual number of input lines (288). A formula to calculate the maximum pan factor is shown below. NoOPL - NoIPL PAN int -------------------------------------------- 4 After some rearranging of the formula we get this simple formula to calculate the maximum register value of the pan factor. NoOPL 16 - ZOOM PAN int -------------------- x ------------------------------ 8 16 where NoIPL: NoOPL: Number of required input lines Number of generated output lines (AL * 2) + 2
Semiconductor Group
22
1998-02-01
SDA 9255
ZOOM: PAN:
Register value (0 ... 16) Register value (0 ... 63)
In the fourth column of table 5 the panning range is shown for NoOPL = 288. If the pan factor is larger than specified in the previous equation, the last input line is used for interpolation of the remaining lines. On the screen the last line is repeated. 2.7
I2C Bus
2.7.1 I2C-Bus Slave Address 1011110 2.7.2 I2C-Bus Format The SDA 9255 I2C-Bus interface acts as a slave receiver and a slave transmitter and provides three different access modes (write, read, continuous read). All modes run with a subaddress auto increment. The interface supports the normal 100 kHz transmission speed as well as the high speed 400 kHz transmission. Write: S10111100A S: A: P: NA: Read: S 1 0 1 1 1 1 0 0 A Subaddress A S 1 0 1 1 1 1 0 1 A Data Byte A
*****
Write Address: BCH Read Address: BDH
Subaddress
A
Data Byte
A
*****
AP
Start condition Acknowledge Stop condition Not Acknowledge
Data Byte
NA
P
Continuous Read: S 1 0 1 1 1 1 0 1 A Data Byte A
*****
Data Byte
NA P
The transmitted data are internally stored in registers. The master has to write a don't care byte to the subaddress FFH (store command) to make the register values available for the SDA 9255. To have a defined time step, where the data will be available, the data are made valid with the incoming V-Sync or with the next SYNC_ST pulse, which is an internal signal and indicates the start of a new output cycle of either four fields in 100/ 120 Hz interlaced mode or two frames in 50/60 Hz proscan mode. The subaddresses, where the data are made valid with the V-Sync (every 20 ms) are indicated in the overview of the subaddresses with V", where the data are made valid with the
Semiconductor Group 23 1998-02-01
SDA 9255
SYNC_ST (every 40 ms) are indicated with S". The 2C-Bus status bits of the SDA 9255 (sub19H, Bit 7; sub1EH, Bit 7) reflect the state of the register values. If these bits are read as '0' then the store command was sent, but the data aren't made available yet. If these bits are '1' then the data were made valid and a new write or read cycle can start. The I2C-Bus status bits have to be checked before writing or reading new data, otherwise data can be lost by overwriting. After switching on the IC, all bits of the SDA 9255 are set to defined states. In particular: Subaddress Default Value 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 6FH 56H 68H 23H 10H 30H 50H not used 61H 74H 8FH 94H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W V V V V Take Over S S V V V V V Subaddress Default Value 0CH 0DH 0EH 0FH 10H 11H ... 18H 19H 1AH ... 1DH 1EH 1FH ... FEH FFH not used not used A2H 50H 2CH 81H 00H not used R/W R/W R/W R/W R/W R/W R/W R R/W R R/W W Take Over V S S S S
R/W: Take over:
R-Read Register, W-Write Register, R/W-Read and Write Register, V-take over with V-Sync, S-take over with SYNC_ST
Semiconductor Group
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1998-02-01
SDA 9255
2.7.3 I2C-Bus Commands
Data Byte Subadd. (Hex.) D7 00H 01H 02H 03H 04H 05H 06H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 19H 1EH FFH
D6
D5 1 0 NRKF00 NRKF20
D4 FREEZE 1 NRKF12 NRKF32
D3 TWOIN 0 NRKF11 NRKF31
D2 TWOOUT
D1 TVMODE1
D0 TVMODE0
MODE10050 1 0 NRKF02 NRKF22 1 NRKF01 NRKF21
MODESYNC1 MODESYNC0 0
NRKF10 NRKF30
x HSINP x x x x VSDLY0 AL1 MCNAPIP5 HSDLY1 INTL2 NAPOP0 x x x x x
x VSINP x x x NRHF x AL0 MCNAPIP4 HSDLY0 INTL1 INTL0 HSODLY x x x x
MDNRTH04 MDNRTH03 MDNRTH02 MDNRTH01 MDNRTH00 x MDNRTH14 MDNRTH13 MDNRTH12 MDNRTH11 MDNRTH10 x MDNRTH24 MDNRTH23 MDNRTH22 MDNRTH21 MDNRTH20 x SNR VSDLY6 AL7 NALIP4 MCNAPIP3 NALOP4 NAPOP6 ZOOM4 PAN5 VSTATUS SSTATUS x FNR1 VSDLY5 AL6 NALIP3 MCNAPIP2 NALOP3 NAPOP5 ZOOM3 PAN4 x x x FNR0 VSDLY4 AL5 NALIP2 MCNAPIP1 NALOP2 NAPOP4 ZOOM2 PAN3 x x x x VSDLY3 AL4 NALIP1 MCNAPIP0 NALOP1 NAPOP3 ZOOM1 PAN2 x x x x VSDLY2 AL3 NALIP0 HSDLY3 NALOP0 NAPOP2 ZOOM0 PAN1 x x x x VSDLY1 AL2 MCNAPIP6 HSDLY2 INTL3 NAPOP1 x PAN0 x x x
x = don't care
Semiconductor Group
25
1998-02-01
SDA 9255
2.7.4 Detailed Description Subaddress 00H Bit D7 Name MODE10050 Function Output mode switch: 0: 100/120 Hz (default value) 1: 50/60 Hz 1: 1: FREEZE Should be set to 1 Should be set to 1
D6 D5 D4
Still picture: 0: Off (default value) 1: On Chrominance input format: 0: Unsigned input (0 ... 255) 1: 2's complement input (-128 ... 127) (default value) Inside the SDA 9255 the data are always processed as unsigned data Chrominance output format: 0: Unsigned output (0 ... 255) 1: 2's complement output (-128 ... 127) (default value) Television system: 00: NTSC (1716) 01: Automatic PAL (n * 32) 10: Automatic NTSC (n * 32 + 20) 11: PAL (1728) (default value) The SDA 9255 is designed for a line-locked system. Therefore the number of system clock periods between two H-Sync (HIN) must be constant. In PAL (1728) mode the number of system clocks (~27.0 MHz) per input line is assumed to be constant 1728. In case of NTSC (1716) mode the number of system clock periods is assumed to be constant 1716. In automatic mode (01 and 10) the number of system clock periods (~27.0 MHz) per incoming line is measured and used to calculate the outgoing line length. In automatic PAL mode the number of system clock periods between two H-Syncs must be n * 32 (n = 1, 2, ..., 54, ...). In automatic NTSC mode the number of system clock periods between two H-Syncs must be n * 32 + 20 (n = 1, 2, ..., 53, ...).
26 1998-02-01
D3
TWOIN
D2
TWOOUT
D1 ... D0 TVMODE
Semiconductor Group
SDA 9255
Subaddress 01H Bit D7 ... D3 D2 ... D1 MODESYNC Name Function Should be set to 01010 Output synchronization mode: 00: Reserved 01: AABB mode for AC coupled vertical deflection, no data shift 10: AABB mode for AC coupled vertical deflection, field 2 and 3 shift down 11: AABB mode for DC coupled vertical deflection (default value) 0: Should be set to 0
D0
Subaddress 02H Bit Name Function Noise Reduction k-factor KF 0: 011: (default value) Noise Reduction k-factor KF 1: 010: (default value) xx D7 ... D5 NRKF0 D4 ... D2 NRKF1 D1 ... D0
Semiconductor Group
27
1998-02-01
SDA 9255
Subaddress 03H Bit Name Function Noise Reduction k-factor KF 2: 001: (default value) Noise Reduction k-factor KF 3: 000: (default value) H-Sync input polarity: 0: Low active 1: High active (default value) V-Sync input polarity: 0: Low active 1: High active (default value) D7 ... D5 NRKF2 D4 ... D2 NRKF3 D1 HSINP
D0
VSINP
Subaddress 04H Bit Name Function Noise Reduction threshold 0: 00010: (default value) xxx D7 ... D3 MDNRTH0 D2 ... D0
Subaddress 05H Bit Name Function Noise Reduction threshold 1: 00110: (default value) xxx D7 ... D3 MDNRTH1 D2 ... D0
Subaddress 06H Bit Name Function Noise Reduction threshold 2: 01010: (default value) xxx D7 ... D3 MDNRTH2 D2 ... D0
Semiconductor Group
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1998-02-01
SDA 9255
Subaddress 08H Bit D7 Name SNR Function Switch for fixed value for motion detection for noise reduction 0: Off (default value) 1: On Fixed value for motion detection for noise reduction 11: (default value) xxxx NRHF Switch for low pass filter for motion detection for noise reduction 0: Off 1: On (default value)
D6 ... D5 FNR D4 ... D1 D0
Subaddress 09H Bit D0 Name Function V-Sync input delay (default value 3AH) x D7 ... D1 VSDLY
Subaddress 0AH Bit Name Function (Number of active input lines per field - 2) / 2 (default value 8FH) D7 ... D0 AL
Subaddress 0BH Bit Name Function Number of not active lines of input data (default value 12H) D7 ... D3 NALIP
D2 ... D0 MCNAPIP6 ... 4 Number of system clocks from internal HS_int to active input data, Bit 6 to 4 (default value 4H)
Semiconductor Group
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1998-02-01
SDA 9255
Subaddress 0CH Bit Name Function D7 ... D4 MCNAPIP3 ... 0 Number of system clocks from internal HS_int to active input data, bit 3 to 0 (default value AH) D3 ... D0 HSDLY H-Sync input delay (default value 2H)
Subaddress 0DH Bit Name Function Number of active lines at output (default value AH) Interlace output for field Bit 3 to 1 (default value 0H) D7 ... D3 NALOP D2 ... D0 INTL3 ... 1
Subaddress 0EH Bit D0 Name INTL0 Function Number of not active pixels at output (default value 16H) Interlace output for field bit 0 (default value 0H) D7 ... D1 NAPOP
Subaddress 0FH Bit D2 ... D1 D0 HSODLY Name Function Zooming factor (default value 10H) xx Delay of H-Sync output (default value 1H) D7 ... D3 ZOOM
Subaddress 10H Bit D1 ... D0 Name Function Panning of the output picture (default value 0H) xx D7 ... D2 PAN
Semiconductor Group
30
1998-02-01
SDA 9255
Subaddress 19H Bit D7 D6 ... D0 Name VSTATUS Function Status bit for subaddresses, which will be made valid by VSync xxxxxxx
Subaddress 1EH Bit D7 D6 ... D0 Name SSTATUS Function Status bit for subaddresses, which will be made valid by SYNC_ST xxxxxxx
Subaddress FFH Bit D7 ... D0 Name Function Store command for all subaddresses, xxxxxxxx
Semiconductor Group
31
1998-02-01
SDA 9255
3
Absolute Maximum Ratings Symbol min. Limit Values max. 70 125 125 260 10 -0.3 -0.3 C C C C s V V V W kV MIL STD 883C method 3015.6, 100 pF, 1500 All inputs/outputs 0 -65 Unit Remark
Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Soldering time Input voltage Output voltage Supply voltages Total power dissipation ESD protection
TA
VDD + 0.3 VDD + 0.3
6 1.2 2
VDD
-0.3 -2
Latch-up protection
-100
100
mA
All voltages listed are referenced to ground (0 V, VSS) except where noted.
Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied.
Semiconductor Group
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1998-02-01
SDA 9255
3.1
Recommended Operating Conditions Symbol min. 4.75 0 2.0 0 2.4 0.4 0.5 27 12 12 5 5 3 0 0 1.3 0.6 0.6 1.3 0.6 100 0
33
Parameter Supply voltages All TTL Inputs H-input voltage L-input voltage All TTL Outputs H-output voltage L-output voltage INPUT/OUTPUT: SDA L-output voltage Clock frequency Low time High time Rise time Fall time H-input voltage
Limit Values nom. 5 25 max. 5.25 70
Unit V C V V V V V MHz ns ns ns ns V V kHz
Remark
VDD Ambient temperature TA VIH VIL VQH VQL VQL
1/T
VDD
0.8
IQH = -2.0 mA IQL = 3.0 mA
at IQL = max see figure 19
Clock TTL Input LL2CLK
tWL tWH tTLH tTHL
I2C Bus (All values are referred to min (VIH) and max (VIL)), fSCL = 400 KHz
VIH L-input voltage VIL SCL clock frequency fSCL Inactive time before tBUF
start of transmission Set-up time start condition Hold time start condition SCL low time SCL high time Set-up time DATA Hold time DATA
VDD
1.5 400
see figure 17 see figure 18
s s s s s
ns
tSU; STA tHD; STA tLOW tHIGH tSU; DAT tHD; DAT
s
1998-02-01
Semiconductor Group
SDA 9255
3.1
Recommended Operating Conditions (cont'd) Symbol min. Limit Values nom. max. 300 300 0.6 900 50 ns ns Unit Remark
Parameter SDA/SCL rise times SDA/SCL fall times Set-up time stop condition Output valid from clock
tR tF tSU; STO tAA
s
ns ns
Input filter spike tSP suppression (SDA and SCL pins) L-output current 3.2
IQL
3
mA
Characteristics (Assuming Recommended Operating Conditions) Symbol min. Limit Values max. 200 mA All VDD pins, typ. 170 mA Unit Remark
Parameter Average supply current Input capacitance
ICC
All Digital Inputs (Including I/O Inputs)
CI Input leakage current II(L)
Set-up time Input hold time Set-up time Input hold time
10 -10 0 25 7 6 10
pF
A
ns ns ns ns
TTL Inputs: YIN, UVIN (Referred to LL2CLK)
tSU tIH tSU tIH
TTL Inputs: HIN, VIN, SYNCEN (Referred to LL2CLK)
TTL Outputs: YOUT, UVOUT, HOUT, VOUT, HREF, INTERLACED (Referred to LL2CLK) Hold time Delay time
tQH tQD
6 25
ns ns
CL = 30 pF
Semiconductor Group
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1998-02-01
SDA 9255
4
Application Information
27.0 MHz CLK
CLK
YI 12 YUV UI 3ADC CSG SDA 9206 12 YUV Scan Rate Converted SDA 9255 27.0 MHz CVBS/ SYNC Display Processor UOUT SDA 9280 VOUT YOUT
HREF
VI
13.5 MHz HIN, VIN
HOUT, VOUT
Figure 6
Semiconductor Group 35 1998-02-01
UES10018
SDA 9255
5 5.1
Waveforms Input Timing of the SDA 9255 (HSINP = 0)
LL2CLK
~ ~
~ ~
t IH
HSIN
t SU
HS_int (HS_DLY x 64 + 4) x t LL2CLK LLCLK
LH_CLK (MC_NAP_OP + 61) x t LL2CLK LQ_CLK
t IH
D/YIN XXXX Y0 t SU C0 Y1 Y2 Y3 Y4
D/UVIN
XXXX (HS_DLY x 64 + MC_NAP_IP + 65) x t LL2CLK
C1
C2
C3
C4
Figure 7
Semiconductor Group 36 1998-02-01
UET10019
SDA 9255
5.2
Output Timing of the SDA 9255
LL2CLK
~ ~
~ ~
HOUT (NAPOP x 4 + 9...12 HSODLY x 172) x t LL2CLK HREF
~ ~
YOUT
Default Value 16
Black
Y0
Y1
Y2
Y3
Y716 Y717 Y718 Y719
Default Value
UET10020 UET10021
~ ~ ~ ~
UVOUT
Default Value 0 (128)
Uncoloured
C0
C1 C2
C3
C716 C717 C718 C719
Default Value
~ ~
Figure 8
5.3
Internal Vertical Synchronization Signal (VSINP = 0)
Field A
Line 625 HS_int VIN
Line 1
Line 2
Line 3
DELAY(VIN to VS_int) VS_int a b a b Sample Points of Field Ident a
Line 313 HS_int VIN
Line 314
Field B
Line 315
Line 316
DELAY(VIN to VS_int) VS_int a b a b a
Figure 9
Semiconductor Group 37 1998-02-01
SDA 9255
5.4
Example for Not Active Input Register
VS_int
Line 625 HN
Line 1
Line 2
Line 3
~ ~
Line 22
Line 23* )
Line 24
Line 25
VS_int
Line 312 HN
Line 313
Line 314
Line 315
~ ~
Line 335
Line 336* )
Line 337
Line 338
UET10022
* ) : First active line of a field
Figure 10
5.5
Example for Not Active Output Register
VOUT
~ ~
HOUT
Line 1
Line 2
Line 3
Line 21
Line 22
Line 23
Line 24
~ ~
HREF
~ ~
First Active Output Line YOUT Default Value 16 Black
~ ~
UVOUT Default Value 0 (2's Complement) or 128 (Unsigned)
Uncoloured
Figure 11
Semiconductor Group 38 1998-02-01
UET10023
~ ~
SDA 9255
5.6
Example for Not Active Output Pixels
LL2CLK
~ ~
HOUT (NAPOP x 4 + 9...12 - HSODLY x 172) x t LL2CLK HREF
t QH t QD
YOUT
Default Value 16
Black
Y0
Y1
Y2
Y3
Y4
Y5
UVOUT
Default Value 0 (128)
Uncoloured
C0
C1
C2
C3
C4
C5
Figure 12
5.7
Timing for HOUT Signal
LL2CLK
HOUT 32 x t LL2CLK
Figure 13
Semiconductor Group 39 1998-02-01
UET10025
UET10024
~ ~
~ ~
SDA 9255
5.8
Timing for VOUT Signal
HOUT
t HOUT
VOUT 2 x t HOUT
Figure 14
5.9
Timing for HREF Signal
LL2CLK
HREF
~ ~
YOUT
16
Y0
Y1
Y2
Y3
Y4
Y713 Y714 Y715 Y716 Y717 Y718 Y719
16
UVOUT
0 (128)
C0
C1
C2
C3
C4
C713 C714 C715 C716 C717 C718 C719 720 x t LL2CLK
0 (128)
Figure 15
Semiconductor Group 40 1998-02-01
UET10027
UET10026
~ ~ ~ ~ ~ ~ ~ ~
SDA 9255
5.10
Example for INTERLACED Signal
VOUT
YUVOUT
FIELD A
FIELD A
FIELD B
FIELD B
FIELD A
INTL0 INTERLACED
INTL1
INTL2
INTL3
INTL0
Figure 16
5.11
I2C-Bus Timing START/STOP
VHYS
SCL
t HD:STA t SU:STA
~ ~
t SU:STO
SDA
START
STOP
UET10029
Figure 17
Semiconductor Group 41 1998-02-01
UET10028
~ ~ ~ ~
SDA 9255
5.12
I2C-Bus Timing DATA
tF
SCL
t LOW
t HIGH
t LOW
tR
t SU:STA t HD:STA
SDA IN
t HD:DAT t SU:DAT
t SU:STO
t SP
SDA OUT
t AA
t AA
t BUF
UET10030
Figure 18
5.13
Timing Diagram Clock
T
t WH
LL2CLK
t WL V IH V IL
t THL
t TLH
Figure 19
Semiconductor Group 42 1998-02-01
UET10031
SDA 9255
6
Package Outlines
P-MQFP-64-1 (Plastic Metric Quad Flat Package)
0.25 min
2.45 max
0.15 +0.08 -0.02
0.88 0.15
2 +0.1 -0.05
H
0.8 0.3
+0.15
12 0.2 17.2 14
1) M
C A-B D C 64x
0.1
0.2 A-B D 64x 0.2 A-B D H 4x D
A
B
64 1 Index Marking
1)
0.6 x 45
GPM05250
Does not include plastic or metal protrusions of 0.25 max. per side
Figure 20
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information".
SMD = Surface Mounted Device Semiconductor Group 43 Dimensions in mm 1998-02-01
14 1) 17.2
7 max

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